Three-dimensional memory device containing source select gate electrodes with enhanced electrical isolation
US9659956B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2016 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Jan 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/50
Abstract
A method of manufacturing a three-dimensional memory device includes forming, a bottom dielectric layer, a bottom sacrificial material layer, and an alternating stack of insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening, forming an epitaxial channel portion and a memory stack structure in the memory opening, forming a backside contact trench, forming a first backside recess by selectively removing the bottom sacrificial material layer, forming a semiconductor oxide layer underneath the bottom dielectric layer and around a material of the epitaxial channel portion, forming second backside recesses by selectively removing the spacer material layers, and forming electrically conductive layers in the first and second backside recesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.