Vertical integration of CMOS electronics with photonic devices
US9659993B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2014 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Sep 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a composite semiconductor structure includes providing an SOI substrate including a plurality of silicon-based devices, providing a compound semiconductor substrate including a plurality of photonic devices, and dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method also includes providing an assembly substrate having a base layer and a device layer including a plurality of CMOS devices, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, and aligning the SOI substrate and the assembly substrate. The method further includes joining the SOI substrate and the assembly substrate to form a composite substrate structure and removing at least the base layer of the assembly substrate from the composite substrate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.