Mechanical stress-decoupling in semiconductor device

US9663354B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Steffen Bieselt · Wehlen, DE
• Dirk Meinhold · Dresden, DE

Key dates

• Filing date: May 14, 2014
• Grant date: May 30, 2017
• Expiry date: Mar 2, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/764
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

According to a method in semiconductor device fabrication, a first trench and a second trench are concurrently etched in a semi-finished semiconductor device. The first trench is a mechanical decoupling trench between a first region of an eventual semiconductor device and a second region thereof. The method further includes concurrently passivating or insulating sidewalls of the first trench and of the second trench. A related semiconductor device includes a first trench configured to provide a mechanical decoupling between a first region and a second region of the semiconductor device. The semiconductor device further includes a second trench and a sidewall coating at sidewalls of the first trench and the second trench. The sidewall coating at the sidewalls of the first trench and at the sidewalls of the second trench are of the same material.