Sharing program interrupt logic in a multithreaded processor

US9665376B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Khary J. Alexander · Poughkeepsie, US
• Michael Billeci · Poughkeepsie, US
• Fadi Y. Busaba · Poughkeepsie, US
• Mark S. Farrell · Pleasant Valley, US
• Christian Jacobi · West Park, US
• Timothy J. Slegel · Staatsburg, US

Key dates

• Filing date: Dec 15, 2014
• Grant date: May 30, 2017
• Expiry date: Nov 22, 2035

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/5005
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In one embodiment, a computer-implemented method includes requesting, by a first processor thread of a computer processor, access to exception tracking logic. The exception tracking logic is accessible by a plurality of processor threads. The first processor thread receives access to the exception tracking logic. The first processor thread executes a process in slow mode. Based on detecting an exception in slow mode, the first processor thread stores, in the exception tracking logic, exception information about the exception. The exception information is copied from the exception tracking logic to a set of external registers outside the exception tracking logic. The exception tracking logic is released to allow access to the exception tracking logic by other processor threads of the plurality of processor threads.