Access methods and circuits for memory devices having multiple banks
US9666255B2 · kind B2 · utility
1Cited by
22References
20Claims
0Family size
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Key dates
| Filing date | Apr 22, 2014 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Apr 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method can include storing a plurality of addresses within one cycle of a timing clock, each address corresponding to a storage location of a memory device; and following the one cycle, accessing a plurality of banks of the memory device in response to the stored addresses corresponding to different banks and preventing access to any one of the plurality of banks by more than one address of the one cycle; wherein each bank includes memory cells arranged into rows and columns that comprise the storage locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.