Contained punch through stopper for CMOS structures on a strain relaxed buffer substrate
US9666486B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2016 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | May 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure is provided in which the diffusion of arsenic is retarded. The structure includes a strain relaxed silicon germanium alloy buffer layer located on a surface of a silicon substrate. A boron-containing p-well region is located in a first region of a carbon doped silicon germanium alloy layer and on a first portion of the strain relaxed silicon germanium alloy buffer layer, and a phosphorus-containing n-well region is located in a second region of the carbon doped silicon germanium alloy layer and on a second portion of the strain relaxed silicon germanium alloy buffer layer. A tensily strained silicon material is located on a surface of the p-well region, and a compressively strained germanium-containing material is located on a surface of the n-well region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.