3DIC structure and method for hybrid bonding semiconductor wafers
US9666566B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2016 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Apr 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/1082
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for improving hybrid bond yield for semiconductor wafers forming 3DIC devices includes first and second wafers having dummy and main metal deposited and patterned during BEOL processing. Metal of the dummy metal pattern occupies from about 40% to about 90% of the surface area of any given dummy metal pattern region. High dummy metal surface coverage, in conjunction with utilization of slotted conductive pads, allows for improved planarization of wafer surfaces presented for hybrid bonding. Planarized wafers exhibit minimum topographic differentials corresponding to step height differences of less than about 400 Å. Planarized first and second wafers are aligned and subsequently hybrid bonded with application of heat and pressure; dielectric-to-dielectric, RDL-to-RDL. Lithography controls to realize WEE from about 0.5 mm to about 1.5 mm may also be employed to promote topographic uniformity at wafer edges. Improved planarity of wafers presented for hybrid bonding results in improved bond uniformity for 3DIC devices formed thereby.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.