3D IC testing apparatus
US9671457B2 · kind B2 · utility
4Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2014 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Apr 28, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/30
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method comprises connecting a testing setup having a plurality of probes to a device under test having a plurality of vias, wherein a probe is aligned with a corresponding via of the device under test and conducting a plurality of via electrical characteristic tests through a conductive path comprising the vias, the probes and a plurality of conductive devices, each of which connects two adjacent probes, wherein the conductive devices are in the testing setup.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.