Frequency-domain high-speed bus signal integrity compliance model
US9673941B2 · kind B2 · utility
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3References
10Claims
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Key dates
| Filing date | May 26, 2015 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Jun 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide apparatus for testing channel compliance. The apparatus generally performs operations that includes identifying at least one design criteria and determining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. The boundary sets may be used for verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.