Systems and methods involving multi-bank, dual- or multi-pipe SRAMs
US9679631B2 · kind B2 · utility
27Cited by
24References
37Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 24, 2015 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Nov 24, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.