Dual molded stack TSV package
US9679801B2 · kind B2 · utility
15Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2015 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Jun 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Packages including an embedded die with through silicon vias (TSVs) are described. In an embodiment, a first level die including TSVs is embedded between a first redistribution layer (RDL) and a second RDL, and a second level die is mounted on a top side of the first redistribution layer. In an embodiment, the first level die is an active die, less than 50 μm thick.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.