Flip-flop circuit with latch bypass
US9680450B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 19, 2015 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Feb 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one form, a flip-flop comprises a master latch, a slave latch, and a multiplexer. The master latch has an input for receiving a data input signal, and an output, and operates in transparent and latching modes during respective first and second phases of a clock signal. The slave latch has an input coupled to the output of the master latch, and an output, and operates in the transparent and latching modes during the second and first phases of the clock signal, respectively. The multiplexer has a first input coupled to the output of the slave latch, a second input coupled to the output of the master latch, and an output for providing a data output signal, and provides the first input to the output during the first phase of the clock signal, and the second input to the output during the second phase of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.