Fractional and reconfigurable digital phase-locked loop
US9680480B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2016 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Jul 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/22
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reconfigurable digital phase-locked loop integrated circuit is disclosed which is coupleable to a reference frequency generator to generate an input signal having a reference frequency. A representative embodiment of the reconfigurable digital phase-locked loop integrated circuit may include a first digital phase-locked loop circuit configured to generate a first signal having a first frequency which is an integer multiple of the reference frequency; and a second digital phase-locked loop circuit coupled to the first digital phase-locked loop, the second digital phase-locked loop configured to generate a second, output signal having a second output frequency in response to a plurality of configuration parameters, the second frequency having a configurable fractional offset from the integer multiple of the reference frequency, and to match a phase of the second output signal with a first signal phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.