Patent · US Active

De-coupling capacitance placement

US9684759B2 · kind B2 · utility

0Cited by
8References
13Claims
0Family size

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Key dates

Filing dateOct 28, 2015
Grant dateJun 20, 2017
Priority date
Expiry dateOct 28, 2035

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F2119/12
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A method, executed by one or more processors, includes receiving IR-drop information as a function of location for a placement for a plurality of circuit blocks corresponding to an integrated circuit, calculating a target density for decoupling capacitors as a function of location based on the IR-drop information, placing a plurality of decoupling capacitors according to the target density to provide placed decoupling capacitors. The placed decoupling capacitors may be locally clustered to improve decoupling performance. The method may also include incrementally moving circuit elements or placed decoupling capacitors to avoid collisions within one or more circuit blocks, and routing the integrated circuit. A corresponding computer program product and computer system are also disclosed herein.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.