Patent · US Active

Memory cell with read transistors of the TFET and MOSFET type to reduce leakage current

US9685222B2 · kind B2 · utility

1Cited by

2References

10Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Olivier Thomas · Saint-Martin-d'Hères, FR
Costin Anghel · Vanves, FR
Adam Makosiej · Grenoble, FR

Key dates

Filing date	Oct 14, 2015
Grant date	Jun 20, 2017
Priority date	—
Expiry date	Oct 14, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/419
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Memory cell of the SRAM type, including storage transistors forming a memory point for storing a bit and a read port having at least one MOS transistor, a TFET transistor, a power terminal and a read bit line whereof a potential is designed to vary depending on the value of the stored bit, and such that:

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.