Method for forming semiconductor structure
US9685541B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2016 |
| Grant date | Jun 20, 2017 |
| Priority date | — |
| Expiry date | Aug 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a semiconductor structure, including a substrate, having a fin structure disposed thereon, a gate structure, crossing over parts of the fin structure. The top surface of the fin structure which is covered by the gate structure is defined as a first top surface, and the top surface of the fin structure which is not covered by the gate structure is defined as a second top surface. The first top surface is higher than the second top surface, and a spacer covers the sidewalls of the gate structure. The spacer includes an inner spacer and an outer spacer, and the outer pacer further contacts the second top surface of the fin structure directly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.