BBUL top side substrate layer enabling dual sided silicon interconnect and stacking flexibility
US9691728B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2015 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Feb 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1469
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus including a die including a first side and an opposite second side including a device side with contact points; and a build-up carrier including at least one layer of conductive material disposed on a first side of the die, and a plurality of alternating layers of conductive material and dielectric material disposed on the second side of the die, wherein the at least one layer of conductive material on the first side of the die is coupled to at least one of (1) at least one of the alternating layers of conductive material on the second side of the die and (2) at least one of the contact points of the die. A method including forming a first portion of a build-up carrier adjacent one side of a die, and forming a second portion of the build-up carrier adjacent another side of the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.