Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
US9691746B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2014 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Jul 14, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.