Vertical resistor in 3D memory device with two-tier stack
US9691781B1 · kind B1 · utility
32Cited by
6References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 4, 2015 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Dec 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.