Method, apparatus, system for centering in a high performance interconnect
US9692402B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 25, 2014 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Apr 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.