Semiconductor substrate evaluating method, semiconductor substrate for evaluation, and semiconductor device
US9696368B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 25, 2013 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Nov 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
On an EP substrate 1, an EP layer 2 having a conductivity type different from that of the EP substrate 1 is grown. With ion implantation, a well 5 having the same conductivity type as the EP layer 2 is formed, and a channel stop layer 10 is also formed. A dopant having a conductivity type different from that of the well 5 is diffused in the well 5 to form a pn junction 7 in the well 5. A plurality of cells 20 each having the diffusion layer 6 as one electrode and a rear surface 1a as the other electrode are formed as a TEG. Using the TEG, junction leakage currents from two depletion layers, a depletion layer 8 in the well and a depletion layer 4 at an interface between the EP layer 2 and the EP substrate 1, are measured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.