Non-local error detection in processor systems
US9697074B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2014 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Jul 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for delocalizing an error checking on a data in a pipelined processor from the data checked. A first check-data is generated at a first location on a first data. A second location receives the first data and the first check-data. A second check-data is generated on the first data and the first check-data is compared with the second check-data at the second location. A second data is generated from the first data and a third check-data is generated on the second data at the second location. A third check-data is generated on the second data at the second location and the second data is transferred to a third location. The third check-data is transferred to a fourth location. A fourth check-data is generated on the second data and is transferred to the fourth location. The fourth check-data and the third check-data are compared at the fourth location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.