Level faults interception in integrated circuits
US9697310B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 2015 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Dec 9, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/034
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a computerized mechanism for vulnerability evaluation in a layout having circuitry units as interceptors, comprising receiving a layout with interceptors incorporated therein at prearranged positions, virtually inducing faults in the layout by modeling a physical phenomenon that affects timings in the layout, detecting timing violations in the layout responsive to the induced faults based on discrepancies between the timings and provided specifications thereof determining vulnerability of the layout to faults according to detected faults, and wherein the method is performed on an at least one computerized apparatus configured to perform the method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.