Monolithic memory comprising 1T1R code memory and 1TnR storage class memory
US9697874B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2016 |
| Grant date | Jul 4, 2017 |
| Priority date | — |
| Expiry date | Jun 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Providing for a monolithic memory device comprising a combination of a one-transistor, one-resistor (1T1R) memory array, and a one-transistor, multiple-resistor (1TnR, where n is a suitable integer greater than 1) memory array is described herein. By way of example, the monolithic memory device can be a stand-alone device, configured to perform functions in response to predetermined conditions and generate an output(s), or can be a removable device that can be connected to and operable with another device. In various embodiments, the 1TnR array having high memory density can serve as storage class memory (SCM) for the monolithic memory device, and the 1T1R array having high performance and efficacy can serve as code memory. In addition to the foregoing, the 1T1R array and the 1TnR array can be fabricated from at least one common layer or a common processing step, to simplify and lower cost of fabricating disclosed memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.