Pattern placement error compensation layer
US9704807B2 · kind B2 · utility
0Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2015 |
| Grant date | Jul 11, 2017 |
| Priority date | — |
| Expiry date | Nov 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53295
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.