Masking a power state of a core of a processor

US9710041B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Alexander Gendler · Kiryat Motzkin, IL
• Larisa Novakovsky · Haifa, IL
• Krishnakanth V. Sistla · Beaverton, US
• Vivek Garg · San Mateo, US
• Dean Mulla · San Jose, US
• Ashish V. Choubal · Austin, US
• Erik G. Hallnor · Beaverton, US
• Kimberly C. Weier · Austin, US

Key dates

• Filing date: Jul 29, 2015
• Grant date: Jul 18, 2017
• Expiry date: Aug 4, 2035

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D30/50
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.