Method and apparatus for memory aliasing detection in an out-of-order instruction execution platform
US9710389B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2015 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Jan 25, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor and method are described for alias detection. For example, one embodiment of an apparatus comprises: reordering logic to receive a set of read and write operations in a program order and to responsively reorder the read and write operations; adjustment information attachment logic to associate adjustment information with one or more of the set of read and write operations, wherein for a read operation the adjustment information is to indicate a number of write operations which the read operation has bypassed and for a write operation the adjustment information is to indicate a number of read operations which have bypassed the write operation; and out-of-order processing logic to determine whether execution of the reordered read and write operations will result in a conflict based, at least in part, on the adjustment information associated with the one or more reads and writes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.