Patent · US Active

Shadow trim line edge roughness reduction

US9711359B2 · kind B2 · utility

0Cited by
3References
8Claims
0Family size

Assignee

Inventors

Key dates

Filing dateAug 13, 2015
Grant dateJul 18, 2017
Priority date—
Expiry dateAug 13, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/31144
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A method for etching an etch layer in a stack over a substrate wherein the etch layer is under a mask layer which is under a patterned organic mask is provided. The stack and substrate is placed on a support in the plasma chamber. A silicon based layer is deposited in situ over the stack. The silicon based layer is etched to form silicon based sidewalls or spacers on sides of the patterned organic mask. The mask layer is selectively etched with respect to the silicon based sidewalls or spacers, wherein the selectively etching the mask layer undercuts the silicon based sidewalls or spacers. The etch layer is selectively etched with respect to the mask layer. The stack and substrate are removed from the support and the plasma chamber.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.