Self-aligned lithographic patterning with variable spacings
US9711447B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2016 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Oct 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53238
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of lithographic patterning and structures formed by lithographic patterning. A hardmask layer is formed on a dielectric layer, a feature is formed on the hardmask layer, and a mandrel is formed that extends in a first direction across the first feature. The mandrel and the hardmask layer beneath the mandrel are removed to pattern the hardmask layer with the feature masking a section of the hardmask layer. After the hardmask layer is patterned, the dielectric layer is etched to form a first trench and a second trench that are separated by a section of the dielectric layer masked by the section of the hardmask layer. The first trench and the second trench are filled with a conductor layer to respectively form a first wire and a second wire that is separated from the first wire by the section of the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.