Interlayer via

US9711501B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Veeraraghavan S. Basker · Schenectady, US
• Lawrence A. Clevenger · Saratoga Springs, US
• Terence B. Hook · Jericho, US
• Joshua M. Rubin · Albany, US
• Tenko Yamashita · Schenectady, US

Key dates

• Filing date: Sep 26, 2016
• Grant date: Jul 18, 2017
• Expiry date: Sep 26, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/215
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device is provided. The semiconductor device includes a lower layer, an upper layer and an interlayer via. The lower layer includes a lower substrate, lower electronic devices, metallization elements and contact elements. One of the lower electronic devices includes a field effect transistor (FET), lower contacts and spacers interposed between the FET and the lower contacts. At least one of the contact elements is electrically coupled between a metallization element and one of the lower contacts to form a stack. The upper layer includes an upper substrate and upper electronic devices. One of the upper electronic devices includes an FET, upper contacts and spacers interposed between the FET and the upper contacts. The upper substrate and one of the upper contacts define a through-hole aligned with the stack. The interlayer via extends through the through-hole to electrically couple the stack and the one of the upper contacts.