Hierarchical wire-pin co-optimization
US9715572B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2015 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | Oct 9, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system to perform physical synthesis in a chip design process using hierarchical wire-pin co-optimization are described. The method includes providing boundary conditions to each of a plurality of macros of the chip design from a unit level controller, the boundary conditions including initial pin locations and an indication of which of the pins are movable pins for each of the plurality of macros, performing macro-level physical synthesis at each of the plurality of macros, and providing feedback to the unit level controller based on the macro-level physical synthesis performed at each of the plurality of macros, the feedback including a proposed new location for the movable pins of each of the plurality of blocks. The method also includes performing hierarchical co-optimization at the unit level controller based on the feedback from each of the plurality of macros to determine locations for the movable pins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.