Vertical memory devices having dummy channel regions
US9716104B2 · kind B2 · utility
31Cited by
8References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 5, 2016 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | Jan 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/40
Abstract
A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.