FinFET semiconductor devices including recessed source-drain regions on a bottom semiconductor layer and methods of fabricating the same
US9716176B2 · kind B2 · utility
1Cited by
17References
16Claims
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Key dates
| Filing date | Nov 6, 2014 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | Feb 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
Abstract
FinFET semiconductor devices and methods of forming the same are provided. The finFET semiconductor devices may include an insulator layer, a bottom semiconductor layer on the insulator layer, a channel fin on the bottom semiconductor layer, a source region on the bottom semiconductor layer and adjacent a first side of the channel fin, and a drain region on the bottom semiconductor layer and adjacent a second side of the channel fin opposite the first side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.