Patent · US Active

Method of patterning without dummy gates

US9721793B2 · kind B2 · utility

6Cited by

1References

14Claims

0Family size

Assignee

TOKYO ELECTRON LIMITED · JP

Inventors

Jeffrey Smith · Clifton Park, US
Anton J. deVilliers · Boise, US

Key dates

Filing date	Jul 28, 2016
Grant date	Aug 1, 2017
Priority date	—
Expiry date	Jul 28, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/038
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Techniques herein provide precise cuts for fins and nanowires without needing dummy gate pairs to compensate for overlay misalignment. Techniques herein include using an etch mask to remove designated portions of gate structures to define a trench or open space having fin structures, nanowires, etc. The uncovered fin structures are etched away or otherwise removed from the trench segments. The etch mask and material defining the trench provide a combined etch mask for removing uncovered fin portions. Subsequently the trench segments are filled with dielectric material. Without needed dummy gate pairs a given substrate can fit significantly more electrical devices per unit area.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.