Alignment of three dimensional integrated circuit components
US9721855B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2014 |
| Grant date | Aug 1, 2017 |
| Priority date | — |
| Expiry date | Dec 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06593
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for aligning a chip onto a substrate is disclosed. The method includes, depositing a ferrofluid, onto a substrate that has one or more pads that electrically couple to a semiconductor layer. The method can include a chip with solder balls electrically coupled to the logic elements of the chip, which can be placed onto the deposited ferrofluid, where the chip is supported on the ferrofluid, in a substantially coplanar orientation to the substrate. The method can include determining if the chip is misaligned from a desired location on the substrate. The method can include adjusting the current location of the chip in response to determining that the solder balls of the chip are misaligned from the desired location on the pads of the substrate, until the chip is aligned in the desired location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.