Integrated circuit and manufacturing method thereof
US9721883B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2016 |
| Grant date | Aug 1, 2017 |
| Priority date | — |
| Expiry date | Mar 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/68381
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits and manufacturing methods of the same are disclosed. The integrated circuit includes a transistor, a first dielectric layer, an etch stop layer, a first via and a first conductive layer. The first dielectric layer is disposed between the transistor and the etch stop layer. The first via is disposed in the first dielectric layer and the etch stop layer, and electrically connected to the transistor. The first conductive layer is in contact with the first via, wherein the first via is disposed between the first conductive layer and the transistor, and the etch stop layer is aside a portion of the first via adjacent to the first conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.