Efficient address translation caching in a processor that supports a large number of different address spaces
US9727480B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2014 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Dec 2, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes translation-lookaside buffer (TLB) and a mapping module. The TLB includes a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a valid bit vector, wherein each bit of the valid bit vector indicates, for a respective address translation context, the address translation is valid if set and invalid if clear. The TLB also includes an invalidation bit vector having bits corresponding to the bits of the valid bit vector of the plurality of entries, wherein a set bit of the invalidation bit vector indicates to simultaneously clear the corresponding bit of the valid bit vector of each entry of the plurality of entries. The mapping module generates the invalidation bit vector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.