Stable multiple threshold voltage devices on replacement metal gate CMOS devices
US9728462B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2015 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Mar 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is formed on the fin, and an interlayer dielectric layer is formed on the epitaxial layer. Spacers on the fin define the narrow channel and the long channel. A high-k dielectric material is deposited in the narrow and long channels. A metal layer is deposited on the high-k dielectric material in the narrow and long channels. A height of the high-k dielectric material in the narrow channel is recessed. The metal layer is removed from the narrow and long channels. A work function metal is deposited in the narrow and long channels. A gate conduction metal is deposited to fill the narrow channel and long channel. A capping layer is deposited on the top surface of the structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.