Vertical field effect transistors with metallic source/drain regions
US9728466B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2016 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Apr 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices having vertical FET (field effect transistor) devices with metallic source/drain regions are provided, as well as methods for fabricating such vertical FET devices. For example, a semiconductor device includes a first source/drain region formed on a semiconductor substrate, a vertical semiconductor fin formed on the first source/drain region, a second source/drain region formed on an upper surface of the vertical semiconductor fin, a gate structure formed on a sidewall surface of the vertical semiconductor fin, and an insulating material that encapsulates the vertical semiconductor fin and the gate structure. The first source/drain region comprises a metallic layer and at least a first epitaxial semiconductor layer. For example, the metallic layer of the first source/drain region comprises a metal-semiconductor alloy such as silicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.