Three dimensional memory array with select device
US9728584B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2013 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Jun 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines. Storage element material is arranged around the at least one conductive extension, and a select device is arranged around the storage element material. The storage element material is radially adjacent an insulation material separating the plurality of first conductive lines, and the plurality of materials arranged around the storage element material are radially adjacent each of the plurality of first conductive lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.