Integrated device packages having a MEMS die sealed in a cavity by a processor die and method of manufacturing the same
US9731959B2 · kind B2 · utility
1Cited by
32References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2014 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Nov 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An integrated device package is disclosed. The package includes a substrate comprising a cavity through a top surface of the substrate. A first integrated device die is positioned in the cavity. The first integrated device die includes one or more active components. A second integrated device die is attached to the top surface of the substrate and positioned over the cavity. The second integrated device die covers the cavity. Encapsulant can cover the second integrate device die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.