Frequency-domain high-speed bus signal integrity compliance model
US9733305B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2015 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Aug 24, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Embodiments of the present disclosure provide methods for using a compliance model to determine compatibility of a channel with a bus's chip I/O circuitry at its ends. The method includes identifying at least one design criteria and obtaining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. In certain embodiments, the boundary sets may be derived using a genetic algorithm. The method further includes verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.