Fabricating method of semiconductor structure
US9735015B1 · kind B1 · utility
2Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2016 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Dec 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor structure, comprising: providing a preliminary structure having a first region and a second region and comprising a plurality of first trenches in the first region; forming a metal layer filling the first trenches covering on the preliminary structure, wherein the metal layer comprises a concave portion in the second region and the concave portion defines an opening; forming a metal nitride layer on the metal layer by an nitride treatment; and performing a planarization process to remove the metal nitride layer and a portion of the metal layer to expose the preliminary structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.