Semiconductor lead frame, semiconductor package, and manufacturing method thereof
US9735106B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2016 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | May 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor lead frame includes a metal plate and a semiconductor chip mounting area provided on a top surface of the metal plate. A first plating layer for an internal terminal is provided around the semiconductor chip mounting area. A second plating layer for an external terminal is provided on a back surface of the metal plate at a location opposite to the semiconductor chip mounting area. The first plating layer includes a fall-off prevention structure for preventing the first plating layer from falling off from an encapsulating resin when the top surface of the metal plate is encapsulated in the encapsulating resin. The second plating layer does not include the fall-off prevention structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.