Optimized layout for relaxed and strained liner in single stress liner technology
US9735159B2 · kind B2 · utility
1Cited by
1References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 29, 2014 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Dec 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and method with a single stress liner film and a stress relief implant where the distance of the stress relief implant to the transistors is adjusted for improved transistor performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.