Air-gap top spacer and self-aligned metal gate for vertical fets
US9735246B1 · kind B1 · utility
28Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 11, 2016 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | May 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6736
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Transistors and method of forming he same include forming a fin on a bottom source/drain region having a channel region and a sacrificial region on the channel region. A gate stack is formed on sidewalls of the channel region. A gate conductor is formed in contact with the gate stack that has a top surface that meets a middle point of sidewalls of the sacrificial region. The sacrificial region is trimmed to create gaps above the gate stack. A top spacer is formed on the gate conductor having airgaps above the gate stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.