Wire bond through-via structure and method
US9741680B1 · kind B1 · utility
0Cited by
12References
1Claims
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Assignee
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Key dates
| Filing date | Aug 29, 2016 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Aug 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.