Electronic device including a multiple channel HEMT and an insulated gate electrode
US9741840B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2016 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Sep 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
An electronic device can include a lower channel layer, an upper channel layer overlying the lower channel layer and having an opening extending through the upper channel layer. The electronic device can further include an insulator within the opening; and a gate electrode extending into the opening, wherein the insulator is disposed between the gate electrode and the second channel layer. A double channel transistor can include the lower and upper channel layers and the gate electrode. In a further embodiment, a conductive member can be used to electrically short the channel layers near the gate electrode. In an embodiment, the transistor can be enhancement-mode transistor. A process can include forming the insulator such that it is in the form of a sidewall spacer or as an insulating layer along the sidewall and bottom of the opening through the upper channel layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.