Method for fabricating semiconductor package
US9748106B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2016 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Jan 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/11
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor package, the method includes forming at least one conductive via having a first end and a second end opposite the first end in a wafer, in which the wafer has a first surface and a second surface opposite the first surface, and the first end of the at least one conductive via is exposed of the first surface of the wafer; grinding the second surface of the wafer to form an inner portion and a ring portion surrounding the inner portion of the wafer, wherein the inner portion has a thinner thickness than that of the ring portion; and etching the inner portion to expose the second end of the at least one conductive via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.