Method and system for selective spacer etch for multi-patterning schemes
US9748110B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2016 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Aug 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a method for increasing pattern density of a structure on a substrate using an integration scheme, the method comprising: providing a substrate having a first spacer pattern and an underlying layer, the underlying layer comprising a first underlying layer, a second underlying layer, and a target layer; performing a conformal spacer deposition using an oxide, the deposition creating a conformal layer; performing a spacer RIE process and a pull process, thereby generating a second spacer pattern, the spacer RIE process includes adsorption of N-containing gas on a surface of the substrate which activates the surface to react with an F- and/or an H-containing gas to form fluorosilicates; and wherein the integration targets include selectively etching spacer films within a target spacer etch rate, enhanced simultaneous selectivity to the first underlying layer and the second underlying layer and preventing pattern damage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.